Verilog RTL design and verification
517 RTL design and verification problems from real hardware workflows — spec-to-RTL, code completion and modification, module reuse, debugging, testbench generation, and RTL/testbench comprehension Q&A.
Model
Score
Opus 5.5Max
64.1%
Fable 5.1Max
62.6%
Fable 5.1High
61.2%
Opus 5Max
62.2%
Sonnet 5.5Max
60.6%
Muse Wonder 1.0Max
59.2%
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