Verilog RTL design and verification
517 RTL design and verification problems from real hardware workflows — spec-to-RTL, code completion and modification, module reuse, debugging, testbench generation, and RTL/testbench comprehension Q&A.
Model
Score
Fable 5.1Max
61.6%
Fable 5.1High
60.2%
Opus 5Max
61.1%
Grok 4.6xHigh
57.1%
GPT-5.6 SolMax
54.7%
GPT-5.6 SolxHigh
54.1%
Kimi K3Max
54.4%
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